------------------------------------------------------------------------------ -- Confidential Information -- (C) Copyright 2010, Dust Networks Inc. All rights reserved. -- ----------------------------------------------------------------------------- entity ltc5800wr is generic(PHYSICAL_PIN_MAP : string := "QFN72"); ---------------------------- -- Logical Port Descriptions ---------------------------- Port ( RADIO_INHIBIT: INOUT bit; UARTC1_TX: linkage bit; UARTC1_RX: linkage bit; CAP_PA_1P: linkage bit; CAP_PA_1M: linkage bit; CAP_PA_2M: linkage bit; CAP_PA_2P: linkage bit; CAP_PA_3P: linkage bit; CAP_PA_3M: linkage bit; CAP_PA_4M: linkage bit; CAP_PA_4P: linkage bit; VDDPA: linkage bit; LNA_EN: INOUT bit; RADIO_TX: INOUT bit; RADIO_TXn: INOUT bit; ANTENNA: linkage bit; AI_4: linkage bit; AI_0: linkage bit; AI_5: linkage bit; AI_1: linkage bit; AI_3: linkage bit; AI_2: linkage bit; OSC_32K_XOUT: linkage bit; OSC_32K_XIN: linkage bit; VBGAP: linkage bit; RESETn: IN bit; TDI: IN bit; TDO: OUT bit; TMS: INOUT bit; TCK: IN bit; DP4: INOUT bit; OSC_20M_XIN: linkage bit; OSC_20M_XOUT: linkage bit; VDDA: linkage bit; VCORE: linkage bit; VOSC: linkage bit; VPRIME1: linkage bit; DP3: INOUT bit; DP2: INOUT bit; SLEEPn: INOUT bit; DP0: INOUT bit; UARTC0_TX: INOUT bit; UARTC0_RX: INOUT bit; SPIM_MISO: INOUT bit; IPCS_MISO: INOUT bit; SPIM_MOSI: INOUT bit; IPCS_MOSI: INOUT bit; SPIM_SCK: INOUT bit; IPCS_SCK: INOUT bit; SPIM_SS_4n: linkage bit; IPCS_SSn: INOUT bit; SPIM_SS_3n: linkage bit; SPIM_SS_2n: linkage bit; SPIM_SS_1n: INOUT bit; SPIM_SS_0n: INOUT bit; DP1: INOUT bit; PWM0: INOUT bit; SPIS_MISO: INOUT bit; SPIS_MOSI: INOUT bit; SPIS_SCK: INOUT bit; SPIS_SSn: INOUT bit; VPP1: linkage bit; FLASH_P_ENn: INOUT bit; DP5: linkage bit; VPRIME: linkage bit; CAP_PRIME_4P: linkage bit; CAP_PRIME_4M: linkage bit; CAP_PRIME_3M: linkage bit; CAP_PRIME_3P: linkage bit; CAP_PRIME_2P: linkage bit; CAP_PRIME_2M: linkage bit; CAP_PRIME_1M: linkage bit; CAP_PRIME_1P: linkage bit; VSUPPLY1: linkage bit; DP6: linkage bit; VSUPPLY: linkage bit; SDA: linkage bit; SCL: linkage bit; UART_RX_RTSn: IN bit; UART_RX_CTSn: OUT bit; UART_RX: IN bit; UART_TX_RTSn: OUT bit; UART_TX_CTSn: IN bit; UART_TX: INOUT bit; TIMEn: INOUT bit; ); ------------------------- -- Standard Use Statement ------------------------- use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ltc5800wr : entity is "STD_1149_1_1993"; ----------------------------- -- Device Package Pin Mapping ----------------------------- attribute PIN_MAP of ltc5800wr : entity is PHYSICAL_PIN_MAP; constant QFN72 : PIN_MAP_STRING := "RADIO_INHIBIT: 1 , " & "CAP_PA_1P: 2 , " & "CAP_PA_1M: 3 , " & "CAP_PA_2M: 4 , " & "CAP_PA_2P: 5 , " & "CAP_PA_3P: 6 , " & "CAP_PA_3M: 7 , " & "CAP_PA_4M: 8 , " & "CAP_PA_4P: 9 , " & "VDDPA: 10 , " & "LNA_EN: 11 , " & "RADIO_TX: 12 , " & "RADIO_TXn: 13 , " & "ANTENNA: 14 , " & "AI_0: 15 , " & "AI_1: 16 , " & "AI_3: 17 , " & "AI_2: 18 , " & "OSC_32K_XOUT: 19 , " & "OSC_32K_XIN: 20 , " & "VBGAP: 21 , " & "RESETn: 22 , " & "TDI: 23 , " & "TDO: 24 , " & "TMS: 25 , " & "TCK: 26 , " & "DP4: 27 , " & "OSC_20M_XIN: 28 , " & "OSC_20M_XOUT: 29 , " & "VDDA: 30 , " & "VCORE: 31 , " & "VOSC: 32 , " & "DP3: 33 , " & "DP2: 34 , " & "SLEEPn: 35 , " & "DP0: 36 , " & "UARTC0_TX: 37 , " & "UARTC0_RX: 38 , " & "SPIM_MISO: 39 , " & "IPCS_MISO: 40 , " & "SPIM_MOSI: 41 , " & "IPCS_MOSI: 42 , " & "SPIM_SCK: 43 , " & "IPCS_SCK: 44 , " & "IPCS_SSn: 45 , " & "SPIM_SS_1n: 46 , " & "SPIM_SS_0n: 47 , " & "DP1: 48 , " & "PWM0: 49 , " & "SPIS_MISO: 50 , " & "SPIS_MOSI: 51 , " & "SPIS_SCK: 52 , " & "SPIS_SSn: 53 , " & "VPP1: 54 , " & "FLASH_P_ENn: 55 , " & "VPRIME: 56 , " & "CAP_PRIME_4P: 57 , " & "CAP_PRIME_4M: 58 , " & "CAP_PRIME_3M: 59 , " & "CAP_PRIME_3P: 60 , " & "CAP_PRIME_2P: 61 , " & "CAP_PRIME_2M: 62 , " & "CAP_PRIME_1M: 63 , " & "CAP_PRIME_1P: 64 , " & "VSUPPLY1: 65 , " & "VSUPPLY: 65 , " & "UART_RX_RTSn: 66 , " & "UART_RX_CTSn: 67 , " & "UART_RX: 68 , " & "UART_TX_RTSn: 69 , " & "UART_TX_CTSn: 70 , " & "UART_TX: 71 , " & "TIMEn: 72 , " & --------------------------- -- Scan Port Identification --------------------------- attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (5.00000000e+06, BOTH); ---------------------------------------------------------------- -- Insruction register description ---------------------------------------------------------------- attribute INSTRUCTION_LENGTH of ltc5800wr : entity is 4; attribute INSTRUCTION_OPCODE of ltc5800wr : entity is "DIAGNOSE_MBIST (1001)," & "EXTEST (0010)," & "HIGHZ (0101)," & "SAMPLE (0001)," & "LATCR (1100)," & "CONTINUE_MBIST (0111)," & "CLAMP (0100)," & "BYPASS (1111)," & "PRELOAD (0001)," & "RUN_MBIST (0110)"; attribute INSTRUCTION_CAPTURE of ltc5800wr : entity is "0001"; ---------------------------------------------------------------- -- Device ID Code ---------------------------------------------------------------- -- Uncomment lines below if you want to include a device id code -- replace xxxx's with required vendor specific device information -- Make sure IDCODE appears then in the INSTRUCTION_OPCODE description -- Uncomment lines below this: ------------------------------ -- attribute IDCODE_REGISTER of ltc5800wr: entity is -- -- version, part number, manufacturer code, lsb -- "xxxx" & -- "xxxxxxxxxxxxxxxx" & -- "xxxxxxxxxxx" & -- "1"; ---------------------------------------------------------------- -- Device USER Code ---------------------------------------------------------------- -- Uncomment lines below if you want to include a device user code -- replace xxxx's with a <32-bit pattern list string> -- Make sure both IDCODE and USER-CODE appear then in the INSTRUCTION_OPCODE description -- Uncomment lines below this: ------------------------------ -- attribute USERCODE_REGISTER of ltc5800wr: entity is -- --"xxxx" & "xxxx" & "xxxx" & "xxxx" & -- Additional <32-bit pattern> -- "xxxx" & "xxxx" & "xxxx" & "xxxx" ; ---------------------------------------------------------------- -- Register Access Description ---------------------------------------------------------------- attribute REGISTER_ACCESS of ltc5800wr : entity is "BOUNDARY (EXTEST,SAMPLE,PRELOAD), " & "BYPASS (BYPASS,HIGHZ,CLAMP)"; ------------------------------------- -- Boundary-Scan Register Description ------------------------------------- attribute BOUNDARY_LENGTH of ltc5800wr : entity is 80; attribute BOUNDARY_REGISTER of ltc5800wr : entity is ------------------------------------------------------------------------ -- CELL CELL PIN CELL SAFE CNTRL DIS DIS -- # NAME, NAME ,TYPE ,VALU ,CELL ,VAL, RES ------------------------------------------------------------------------ ---------------------------- -- Master Chain [MasterChain1] ---------------------------- "0 (BC_4, RESETn, input, X)," & "1 (BC_5, *, control, 1)," & "2 (BC_7, RADIO_TXn, bidir, X, 1, 1, Z)," & "3 (BC_5, *, control, 1)," & "4 (BC_7, RADIO_TX, bidir, X, 3, 1, Z)," & "5 (BC_5, *, control, 1)," & "6 (BC_7, LNA_EN, bidir, X, 5, 1, Z)," & "7 (BC_3, *, internal, 0)," & "8 (BC_5, *, internal, 0)," & "9 (BC_7, *, internal, 0)," & "10 (BC_5, *, control, 1)," & "11 (BC_7, RADIO_INHIBIT, bidir, X, 10, 1, Z)," & "12 (BC_5, *, control, 1)," & "13 (BC_7, TIMEn, bidir, X, 12, 1, Z)," & "14 (BC_5, *, control, 1)," & "15 (BC_7, UART_TX, bidir, X, 14, 1, Z)," & "16 (BC_3, UART_TX_CTSn, input, X)," & "17 (BC_1, UART_TX_RTSn, output2, X)," & "18 (BC_3, UART_RX, input, X)," & "19 (BC_1, UART_RX_CTSn, output2, X)," & "20 (BC_3, UART_RX_RTSn, input, X)," & "21 (BC_5, *, internal, 0)," & "22 (BC_7, *, internal, 0)," & "23 (BC_5, *, internal, 0)," & "24 (BC_7, *, internal, 0)," & "25 (BC_5, *, internal, 0)," & "26 (BC_7, *, internal, 0)," & "27 (BC_5, *, internal, 0)," & "28 (BC_7, *, internal, 0)," & "29 (BC_5, *, control, 1)," & "30 (BC_7, FLASH_P_ENn, bidir, X, 29, 1, Z)," & "31 (BC_5, *, control, 1)," & "32 (BC_7, SPIS_SSn, bidir, X, 31, 1, Z)," & "33 (BC_5, *, control, 1)," & "34 (BC_7, SPIS_SCK, bidir, X, 33, 1, Z)," & "35 (BC_3, SPIS_MOSI, input, X)," & "36 (BC_5, *, control, 1)," & "37 (BC_7, SPIS_MISO, bidir, X, 36, 1, Z)," & "38 (BC_5, *, control, 1)," & "39 (BC_7, PWM0, bidir, X, 38, 1, Z)," & "40 (BC_5, *, control, 1)," & "41 (BC_7, DP1, bidir, X, 40, 1, Z)," & "42 (BC_5, *, control, 1)," & "43 (BC_7, SPIM_SS_0n, bidir, X, 42, 1, Z)," & "44 (BC_5, *, control, 1)," & "45 (BC_7, SPIM_SS_1n, bidir, X, 44, 1, Z)," & "46 (BC_5, *, internal, 0)," & "47 (BC_7, *, internal, 0)," & "48 (BC_5, *, internal, 0)," & "49 (BC_7, *, internal, 0)," & "50 (BC_5, *, control, 1)," & "51 (BC_7, IPCS_SSn, bidir, X, 50, 1, Z)," & "52 (BC_5, *, internal, 0)," & "53 (BC_1, *, internal, 0)," & "54 (BC_5, *, control, 1)," & "55 (BC_7, IPCS_SCK, bidir, X, 54, 1, Z)," & "56 (BC_5, *, control, 1)," & "57 (BC_7, SPIM_SCK, bidir, X, 56, 1, Z)," & "58 (BC_5, *, control, 1)," & "59 (BC_7, IPCS_MOSI, bidir, X, 58, 1, Z)," & "60 (BC_5, *, control, 1)," & "61 (BC_7, SPIM_MOSI, bidir, X, 60, 1, Z)," & "62 (BC_5, *, control, 1)," & "63 (BC_7, IPCS_MISO, bidir, X, 62, 1, Z)," & "64 (BC_5, *, control, 1)," & "65 (BC_7, SPIM_MISO, bidir, X, 64, 1, Z)," & "66 (BC_5, *, control, 1)," & "67 (BC_7, UARTC0_RX, bidir, X, 66, 1, Z)," & "68 (BC_5, *, control, 1)," & "69 (BC_7, UARTC0_TX, bidir, X, 68, 1, Z)," & "70 (BC_5, *, control, 1)," & "71 (BC_7, DP0, bidir, X, 70, 1, Z)," & "72 (BC_5, *, control, 1)," & "73 (BC_7, SLEEPn, bidir, X, 72, 1, Z)," & "74 (BC_5, *, control, 1)," & "75 (BC_7, DP2, bidir, X, 74, 1, Z)," & "76 (BC_5, *, control, 1)," & "77 (BC_7, DP3, bidir, X, 76, 1, Z)," & "78 (BC_5, *, control, 1)," & "79 (BC_7, DP4, bidir, X, 78, 1, Z)"; ---------------------------- -- Master Chain ---------------------------- end ltc5800wr;